1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor memory device and, more particularly, to a method for manufacturing a DRAM memory cell of a stack type having a memory capacitance layer formed over a switching transistor.
2. Description of the Prior Art
A memory cell for a high density dynamic RAM has been realized by a so called "one transistor and one capacitor" memory cell which comprises one transistor and one memory capacitance. Since this memory cell is characterized by a small number of constructing parts and the cell area thereof can be easily miniaturized, this type of memory cell has been widely used. To accomplish the requirement for making the memory cell smaller, a memory cell of a stack type in which a memory capacitance is formed over a switching transistor is expected to be one of the major cells to be further developed.
FIG. 2 is a top plan view of a semiconductor memory device. FIGS. 4 and 5 are cross-sectional views taken along a line A--A shown in FIG. 2, respectively, and particularly illustrate the prior art manufacturing steps of the device.
A prior art method of a first type is disclosed in Japanese Patent application Ser. No. Hei 2-207442 and is explained with reference of FIGS. 2 and 4.
In FIGS. 2 and 4, an active region 21 of a switching transistor is isolated electrically by a silicon oxide film 22. On this active region 21, a word line 20, a bit line 6, an electric charge storage electrode 9, a capacitance insulating film 10 and a plate electrode 11 are formed sequentially thereon in this order. The active region 21 is connected electrically to the bit line 6 through a bit line contact 22 and to the electric charge storage electrode 9 through an electric charge storage electrode contact 23, respectively.
Referring to FIG. 4(a), the silicon oxide film 2 is formed on a P-type semiconductor substrate 1 by a LOCOS method. After that, the switching transistor and the bit line 6 are formed in accordance with the known method. A reference numeral 7 designates an n.sup.+ type diffusion layer acting as a source/drain of the switching transistor and a reference numeral 3 designates a first insulating film.
In this process, the bit line is apt to be bared by misalignment of the mask in the lithography process as the device is miniaturized more and more. To avoid this problem, after covering the opening 13 by a second insulating film 8, as shown in FIG. 4(b), the electric charge storage electrode 9 is formed, as shown in FIG. 4(c).
Next, a second prior art method is explained with reference to FIG. 5. There have been proposed some structures which utilize bottom surfaces of respective charge storage electrodes for electrode surfaces in order to obtain a reasonable capacitance while miniaturizing devices. As an example of such structures, there has been a method in which a part of a first insulating film 3 is removed by wet etching with use of a solvent of hydrofluoric acid and, thereby, a space is maintained between the first insulating film 3 and a charge storage electrode 9.
As shown in FIG. 5(a), after depositing a silicon nitride film as a second insulating film 8 and a silicon oxide film as a third insulating film 31 on the first insulating film successively, the third, second and first insulating films 31, 8 and 3 are removed by anisotropy etching using a resist pattern 17 as a mask to form an opening 13. Next, as shown in FIG. 5(b), side walls are formed by a fourth insulating film to guarantee insulation between a bit line 6 and an electric charge storage electrode to be formed later. Thereafter, after depositing polycrystalline silicon as a first conductive film 32, as shown in FIG. 5(c), a patterning for forming the electric charge storage electrodes is carried out, as shown in FIG. 5(d). Then, the silicon oxide film as the third insulating film 31 is removed using a solvent of hydrofluoric acid to form a space 14 between the bottom surface of the charge storage electrode 9 and the second insulating film 8 and, by utilizing the surface of the charge storage electrode bared by the space 14 as an electrode, a reasonable capacitance can be obtained.
However, the conventional methods as stated above have problems as follows.
At first, in the first prior art method, if a width of an bared portion of the bit line 6 is larger than the thickness of the second insulating film 8, that portion is not covered completely by the second insulating film 8 and, accordingly, the bit line 6 is short circuited to the electric charge storage electrode 9 through an uncovered portion 15 of the bit line 6 as indicated by a reference numeral 16 in FIG. 4(c).
In the second prior art method, there is such a possibility that the first insulating film 3 may be etched through the side wall as the fourth insulating film 33 upon wet-etching the same and, thereby, the bit line 6 can be bared again, as shown in (e) of FIG. 5. When the capacitor insulating film and plate electrode are formed as usual, the stability of the device is lowered due to an increase of the capacitance between the bit line and the plate electrode.